ASoC: SOF: refine interrupt function on BDW & HSW

[RanderWang]

This patch follows commit:

ASoC: SOF: byt: fix IPC handled wrong issue(thesofproject/sof@4734afb)

Align with apl/cnl, to fix the issue with dmesg shows "error: rx list
empty but received ...", add mask check for interrupt handling.

two special change:
(1) remove memory read in IRQ function, it be done in ipc_msgs_rx
So this memory read is duplicated.

(2) msg id is stored in ipcx not in hdr. Now we set zero in ipcx
and hdr is zero, so no problem is found.

Test on BDW, pass.

Signed-off-by: Keyon Jie yang.jie@linux.intel.com
Signed-off-by: Rander Wang rander.wang@linux.intel.com

[RanderWang]

@plbossart I know you are curious about why msg is zero in IPCX on BDW. This is caused by our imperfect design of msg_id. our msg_id is a 32bit cmd. On APL msg_id is set like:

u32 cmd = msg->header;
/* send IPC message to DSP */
hda_dsp_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
		      msg->msg_size);
snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
		  cmd | HDA_DSP_REG_HIPCI_BUSY);

It is lucky that cmd never overwrite some bits on APL, CNL, BYT, but on BDW it would overwrite SHIM_IPCX_DONE. This makes interrupt out of order. So that is why we don't set msg_id in SHIM_IPCX.

Actually msg_id is not useful now, so IPC works on BDW

[plbossart]

@RanderWang I didn't understand your explanations but will give you the benefit of doubt. Can you please rebase since there are conflicts with Keyon's cleanup

[RanderWang]

Test and update the PR , it works on BDW.

The msg_id issue is a little obscure, I also spent some time to find this. Just talk about APL.

snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
cmd | HDA_DSP_REG_HIPCI_BUSY);

HDA_DSP_REG_HIPCI is a 32bit register and only the 32th bit, named HDA_DSP_REG_HIPCI_BUSY, is used and other bits is unused. So we use other bits to take msg_id which uses LSB 31bits and let the 32th bit untouched. But on BDW, the 31th bit, named SHIM_IPCX_DONE, is used for IPC. So msg_id would overwrite this bit.

[RanderWang]

And I think the difference between bdw_send_msg and hda_dsp_ipc_send_msg, byt_send_msg is obscure, Someone in open source community may report a bug. I think we should refine the msg id.
Actually, the idea of msg id is out of date, we don't need it now. First it is used to identify multi-thread IPC msg, but later we found that IPC message should be serialized. Now there is only one msg in each transaction, so we don't need msg id to get the correct message.

[bardliao]

@RanderWang We may need msg id if we implement compound ipc in the future.

[RanderWang]

@RanderWang We may need msg id if we implement compound ipc in the future.

yes, but not set msg id in a 32bit register

[plbossart]

@RanderWang if you believe the IPC definition is incorrect/confusing/suboptimal, please file a separate issue and suggest a fix. It's very difficult to follow your line of thought and what exactly you are referring to. Thanks!