support the new stm32L5xx serie #1249
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[L5] sort version.md files commit have to be split and merged with the HAL and CMSIS.
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[L5] sort version.md files commit be splitted and merged with the HAL and CMSIS |
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setting the Vddio2 Independent I/Os supply is required to have LPUART1 Tx/Rx pins on PG7/PG8 |
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Included in STM32CubeL5 FW v1.3.1 Signed-off-by: Francois Ramu <francois.ramu@st.com>
Included in STM32CubeL5 FW v1.3.1 Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
CMSIS Cortex-M33 Device Peripheral Access Layer System Source File to be used in non-secure application when the system implements the TrustZone-M security. Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com> Co-authored-by: Frederic.Pillon <frederic.pillon@st.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com> Co-authored-by: Frederic.Pillon <frederic.pillon@st.com>
Similar to the STM32L4xx serie Signed-off-by: Francois Ramu <francois.ramu@st.com>
This bit is mandatory to use PG[15:2]. Especially for LPUART1 TxRx pins. This bit of the PWR CR2 is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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add the new stm32L5xx series of Ultra-low-power MCUs
Ultra-low-power with FPU Arm Cortex-M33 with Trust Zone, MCU 110 MHz with 512 kbytes of Flash .
https://www.st.com/en/microcontrollers-microprocessors/stm32l5-series.html
Note that TZ mode is not supported in this PR (TZEN = 0)
From STM32CubeL5 release 1.3.1
Signed-off-by: Francois Ramu francois.ramu@st.com